There has been much written about the use of processor models to assist in the development of software. Back in the 1970′s the early versions of Unix on a PDP11 included a simulator of the Motorola 6800 – one of the first Instruction Set Simulators made readily available. It ran very slowly and its focus was to explore the details of the instructions. Today processor models and simulators can have various usage targets.
The models listed on this site, riscv-tools.com, with title ‘Tools for RISCV’ and tagline ‘The Imperas RISCV Tools’, are all available from OVP and are written to be Instruction Accurate and are targeting the development of embedded software. Please search elsewhere for models to be used to test pipelines, cache behaviors, branch predictors and other aspects such as low level cycle/cache performance of CPU architectures.
These Information pages list some of the relevant companies, organizations, and players in the CPU modeling and Virtual Platforms ecosystem.
The Information menu above provides access to several pages of information:
The page information/using-fast-risc-v-cpu-models-in-c-platforms/ provides information and links about how to use the OVP Fast RISC-V Processor Models in C Platforms.
The page information/using-risc-v-systemc-tlm2-processor-models/ provides information and links about how to use the OVP RISC-V Fast Processor Models in SystemC with TLM2.
The page information/using-a-risc-v-instruction-set-simulator-iss/ provides information and links about how to use the RISC-V Instruction Set Simulator (ISS).
The page information/using-risc-v-with-continuous-integration/ provides information and links about how to use the RISC-V Fast processor models with Continuous Integration and Continuous Test methodologies.
The page information/downloading-the-risc-v-models/ introduces how to get the RISC-V models and install/use them.
The links page provides links and information on the RISC-V Fast CPU Models and Virtual Platform ecosystem..
Currently available Fast Processor Model Families.